A Straightforward - Fractional-N Phase-Locked Loop HDL Design for RF Applications
نویسندگان
چکیده
The present paper describes a systematic straightforward design of a - fractional-N PhaseLocked Loop based on HDL behavioral modeling. The proposed design consists in describing the mixed mode behavior of this - fractional-N PLL architecture starting from the specifications of each building block. The HDL models of critical PLL blocks have been described in VHDL-AMS to predict the different over-all specifications. The effect of different noise sources has been accurately introduced to study the PLL system performances. The obtained results are compared with transistor-level simulations to validate the effectiveness of the proposed models. Key-Words: Phase-locked loop (PLL), Frequency synthesizer, Fractional-N, HDL models, Wireless
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